Very Large Scale Integration (VLSI) — Internship Tasks

Objective, Features, Technologies and 4 hands-on tasks to build VLSI fundamentals

Objective

Provide interns with hands-on experience in digital VLSI design flow — from RTL design and simulation to synthesis, verification, and basic physical design checks. Emphasis on low-power, timing closure, and testability.

Features

Technologies & Tools

Verilog / SystemVerilog Cadence / Synopsys ModelSim / VCS SPICE / NGSPICE Primetime (STA)

Tasks (4)

Note: Out of the 4 tasks given, you are required to complete any 3 tasks.

Goal

Write RTL for a small digital block (e.g., 8-bit ALU or simple RISC datapath) and verify functionality with testbenches.

Requirements
  • Create synthesizable Verilog/SystemVerilog modules
  • Write comprehensive testbench with directed and random tests
  • Simulate using ModelSim/GTKWave or any simulator
Deliverables
  1. RTL source files and testbench
  2. Simulation wave screenshots and short explanation of coverage

Goal

Synthesize RTL to a gate-level netlist using an academic flow or open-source tool and perform gate-level simulation.

Requirements
  • Use Synopsys DC / Yosys (open-source) for synthesis
  • Generate netlist and perform gate-level simulation with timing if available
  • Compare RTL vs gate-level behavior
Deliverables
  1. Synthesis script & generated netlist
  2. Simulation logs showing equivalence

Goal

Run basic STA (clock, setup/hold checks) on synthesized netlist using timing libraries or representative delays.

Requirements
  • Prepare timing constraints (SDC) — clocks, I/O delays
  • Use PrimeTime / open-source alternatives for STA
  • Identify timing violations and propose fixes (pipelining, re-synthesis)
Deliverables
  1. Timing report with worst negative slack (if any)
  2. Short write-up describing steps to fix violations

Goal

Introduce Design for Testability (scan insertion) and understand layout vs schematic checks (LVS/DRC) at a conceptual or tool-driven level.

Requirements
  • Apply basic scan chain insertion using DFT tool or describe manual approach
  • Explain LVS/DRC steps and, if tools available, run checks on a sample layout
  • Discuss test coverage and stuck-at faults
Deliverables
  1. DFT plan and any scripts used (or a detailed report if tool not available)
  2. Report describing LVS/DRC steps and outcomes
Suggested duration: 4–8 weeks for the full set (can be split into milestones).

How to Submit Your Tasks

  1. For each task:
    • Create a separate document (DOC, DOCX, or PDF) for each task (Task 1, Task 2, Task 3, Task 4).
    • Add all required screenshots, code snippets, commands, and links as per the deliverables.
  2. Upload your documents:
    • Upload each task document to Google Drive or GitHub (create a public repository or shareable folder).
    • Make sure the sharing permissions allow anyone with the link to view your files.
  3. Submit your links:
    • Copy the public links for each task document.
    • Go to the Task Submission page.
    • Paste your document links in the submission form, clearly mentioning the task number for each link.

Tip: Organize your files and links clearly for faster review and feedback!